Search - FPGA DDS

[VHDL-FPGA-Verilog] DDS

Description: 基于FPGA的DDS直接信号合成器，基于Altera CYcloneII系列-DDS direct FPGA-based signal synthesis, based on Altera CYcloneII Series
Platform: | Size: 949248 | Author: 郭强 | Hits:

[VHDL-FPGA-Verilog] DDS-TEST-4

Description: 用FPGA实现DDS，有正弦，三角，方波，方波可调占空比，频率可调。能做到100K左右。-Using FPGA DDS, a sine, triangle, square, adjustable duty cycle square wave, frequency adjustable. Can do about 100K.
Platform: | Size: 381952 | Author: 刘懿锋 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 关于用FPGA制作的DDS源代码。用的是verilog语言，用的是xlinx的软件-Produced with the DDS on FPGA source code. Using verilog language, using xlinx software
Platform: | Size: 5120 | Author: 张君 | Hits:

[VHDL-FPGA-Verilog] DDS-in-Verilog

Description: Verilog编写基于FPGA的DDS实现，内含源代码，希望对大家有所帮助。-DDS in Verilog FPGA-based implementation, including source code, we want to help.
Platform: | Size: 464896 | Author: haby | Hits:

[VHDL-FPGA-Verilog] FPGA_DDS

Description: FPGA中实现信号发生器,即DDS,代码简洁,精练,非常适合学习,已经经过验证.-The FPGA signal generator, or DDS, the code simple, concise, very suitable for learning, has been verified.
Platform: | Size: 683008 | Author: 刘成岩 | Hits:

[VHDL-FPGA-Verilog] FPGA-DDS

Description: 这个是FPGA 如何实现DDS的一篇论文，希望对你有帮助 -FPGA how to implement the DDS paper, hoping to help you
Platform: | Size: 402432 | Author: gonglex | Hits:

[VHDL-FPGA-Verilog] DDS

Description: DDS信号源项目总结，本文是基于FPGA的DDS设计，采用的是SPCE061A单片机的AD9851模块-DDS signal source project summary，This article is based on the FPGA DDS design, using SPCE061A microcontroller AD9851module
Platform: | Size: 155648 | Author: 王 | Hits:

[VHDL-FPGA-Verilog] dds-dingcengmokuai

Description: ＦＰＧＡ　ＤＤＳ顶层模块基于FPGA的dds ip核的实现，对于学习通信专业的人应该有些帮助-FPGA DDS 顶层模块
Platform: | Size: 5120 | Author: ella | Hits:

[VHDL-FPGA-Verilog] FPGA--DDS

Description: 文章介绍了用FPGA实现DDS的各个功能模块，实现与DDS相同的功能。-This paper introduced the method of using FPGA to instead DDS that have the same function.
Platform: | Size: 275456 | Author: 陈楠 | Hits:

[VHDL-FPGA-Verilog] dds_quicklogic-FPGA

Description: dds_quicklogic FPGA DDS信号源-dds_quicklogic FPGA
Platform: | Size: 67584 | Author: zhaochao | Hits:

[VHDL-FPGA-Verilog] dds(9854)_test(sin_cos)(EP1C6)

Description: 通过FPGA控制DDS(AD9854)输出120M一下的双路正交信号，实现在通信和控制领域的应用。-Controlled by FPGA DDS (AD9854) output 120 m the dual orthogonal signal, realize the application in the field of communication and control.
Platform: | Size: 120832 | Author: yanghang | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 基于FPGA的DDS波形发生模块，频率相位可调-Module based on FPGA DDS waveform，Adjustable frequency phase
Platform: | Size: 117760 | Author: 常云鹏 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: DDS的核心是相位累加器，相位累加器有一个累加器和相位寄存器组成，它的作用是再基准时钟源的作用下进行线性累加，当产生溢出时便完成一个周期，即DDS的一个频率周期。加载Matlab 产生的波形，通过FPGA输出DDS信号-Core DDS is the phase accumulator, a phase accumulator and phase accumulator registers, its role is to carry out a linear accumulation under another reference clock source role overflow when they complete a cycle, a cycle frequency of DDS . Matlab load waveform generated by FPGA DDS output signal
Platform: | Size: 926720 | Author: wangfeng | Hits:

[Other] DDS

Description: 本代码可以实现基于FPGA的DDS系统设计，实现效果好-This code can be realized based on FPGA DDS system design, implementation effect is good
Platform: | Size: 7999488 | Author: 刘玉媛 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: FPGA基于FPGA的DDS设计verilog程序-FPGA DDS project verilog procedure
Platform: | Size: 10240 | Author: 吴汉 | Hits:

[VHDL-FPGA-Verilog] dds

Description: 已实际测试 FPGA 实现 DDS程序-FPGA DDS
Platform: | Size: 2106368 | Author: 熊小卡 | Hits:

[Other] DDS

Description: FPGA DDS的控制，可以用modelsim直接仿真，观察信号。-DDS of FPGA,able to simulate with modelsim and check the signal
Platform: | Size: 23346176 | Author: terran2831 | Hits:

[Other] bishe

Description: DDS(dds)
Platform: | Size: 116736 | Author: 萨达1231 | Hits:

[VHDL-FPGA-Verilog] dds1

Description: 通过FPGA实现的，dds数字信号发生器，可产生正弦波，方波，锯齿波，三角波(DDS digital signal generator through FPGA, DDS digital signal generator, can produce sine wave, square wave, sawtooth wave, triangle wave)
Platform: | Size: 9141248 | Author: 灏浩东 | Hits:

[VHDL-FPGA-Verilog] src

Description: 使用FPGA+DAC产生DDS，可变频率(user FPGA and DAC generate DDS)
Platform: | Size: 29696 | Author: WOO8 | Hits:

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[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] DDS-TEST-4

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] DDS-in-Verilog

[VHDL-FPGA-Verilog] FPGA_DDS

[VHDL-FPGA-Verilog] FPGA-DDS

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] dds-dingcengmokuai

[VHDL-FPGA-Verilog] FPGA--DDS

[VHDL-FPGA-Verilog] dds_quicklogic-FPGA

[VHDL-FPGA-Verilog] dds(9854)_test(sin_cos)(EP1C6)

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] DDS

[Other] DDS

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] dds

[Other] DDS

[Other] bishe

[VHDL-FPGA-Verilog] dds1

[VHDL-FPGA-Verilog] src

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